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| 19-3173; Rev 0; 5/04 KIT ATION EVALU ILABLE AVA Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards General Description The MAX8550A integrates a synchronous-buck PWM controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT, and a 10mA reference output buffer to generate VTTR. The buck controller drives two external n-channel MOSFETs to generate output voltages down to 0.7V from a 2V to 28V input with output currents up to 15A. The LDO can sink or source up to 1.5A continuous and 3A peak current. Both the LDO output and the 10mA reference buffer output can be made to track the REFIN voltage. These features make the MAX8550A ideally suited for DDR memory applications in desktops, notebooks, and graphic cards. The PWM controller in the MAX8550A utilizes Maxim's proprietary Quick-PWMTM architecture with programmable switching frequencies of up to 600kHz. This control scheme handles wide input/output voltage ratios with ease and provides 100ns response to load transients while maintaining high efficiency and a relatively constant switching frequency. The MAX8550A offers fully programmable UVP/OVP and skip-mode options ideal in portable applications. Skip mode allows for improved efficiency at lighter loads. The VTT and VTTR outputs track to within 1% of VREFIN / 2. The high bandwidth of this LDO regulator allows excellent transient response without the need for bulk capacitors, thus reducing cost and size. The buck controller and LDO regulators are provided with independent current limits. Adjustable lossless foldback current limit for the buck regulator is achieved by monitoring the drain-to-source voltage drop of the low-side MOSFET. Additionally, overvoltage and undervoltage protection mechanisms are built in. Once the overcurrent condition is removed, the regulator is allowed to enter soft-start again. This helps minimize power dissipation during a short-circuit condition. The MAX8550A allows flexible sequencing and standby power management using the SHDN and STBY inputs, which support all DDRs' operating states. The MAX8550A is available in a small 5mm x 5mm, 28pin thin QFN package. Features Buck Controller Quick-PWM with 100ns Load-Step Response Up to 95% Efficiency 2V to 28V Input Voltage Range 1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable Output Up to 600kHz Selectable Switching Frequency Programmable Current Limit with Foldback Capability 1.7ms Digital Soft-Start Independent Shutdown and Standby Controls Overvoltage/Undervoltage-Protection Option Power-Good Window Comparator LDO Section Fully Integrated VTT and VTTR Capability VTT Has 3A Sourcing/Sinking Capability VTT and VTTR Outputs Track VREFIN / 2 MAX8550A All-Ceramic Output-Capacitor Designs 1.0V to 2.8V Input Voltage Range Power-Good Window Comparator Ordering Information PART MAX8550AETI TEMP RANGE -40C to +85C PIN-PACKAGE 28 TQFN 5mm x 5mm Pin Configuration AVDD SKIP GND TPO VDD TOP VIEW 28 27 26 25 24 23 PGND1 SHDN 22 TON OVP/UVP REF ILIM POK1 POK2 STBY 1 2 3 4 5 6 7 10 11 12 13 14 8 9 21 20 19 DL BST LX DH VIN OUT FB MAX8550A 18 17 16 15 Applications DDR I and DDR II Memory Power Supplies Desktop Computers Notebooks and Desknotes Graphic Cards Game Consoles RAID Networking PGND2 VTTS VTTR VTTI VTT SS 5mm x 5mm Thin QFN Typical Operating Circuit appears at end of data sheet. Quick-PWM is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products REFIN 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A ABSOLUTE MAXIMUM RATINGS VIN to GND .............................................................-0.3V to +30V VDD, AVDD , VTTI to GND .........................................-0.3V to +6V SHDN, REFIN to GND ..............................................-0.3V to +6V SS, POK1, POK2, SKIP, ILIM, FB to GND ................-0.3V to +6V STBY, TON, REF, UVP/OVP to GND ........-0.3V to (AVDD + 0.3V) OUT, VTTR to GND ..................................-0.3V to (AVDD + 0.3V) DL to PGND1..............................................-0.3V to (VDD + 0.3V) DH to LX ....................................................-0.3V to (VBST + 0.3V) LX to BST..................................................................-6V to +0.3V LX to GND .................................................................-2V to +30V VTT to GND...............................................-0.3V to (VVTTI + 0.3V) VTTS to GND............................................-0.3V to (AVDD + 0.3V) PGND1, PGND2, TP0 to GND ...............................-0.3V to +0.3V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin 5mm x 5mm TQFN (derate 35.7mW/C above +70C).................................................................2.86W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER MAIN PWM CONTROLLER Input Voltage Range Output Adjust Range Output Voltage Accuracy (Note 2) Soft-Start Ramp Time tSS VIN VDD, AVDD VOUT FB = OUT FB = GND FB = VDD Rising edge of SHDN to full current limit TON = GND (600kHz) On-Time tON VIN = 15V, VOUT = 1.5V (Note 3) (Note 3) SHDN = GND IAVDD All on (PWM, VTT, and VTTR on) STBY = GND (only VTTR and PWM on) SHDN = GND Rising edge of VIN Hysteresis IVDD Set VFB = 0.8V 4.05 TON = REF (450kHz) TON = OPEN (300kHz) TON = AVDD (200kHz) Minimum Off-Time VIN Quiescent Supply Current VIN Shutdown Supply Current AVDD Quiescent Supply Current AVDD + VDD Shutdown Supply Current AVDD Undervoltage-Lockout Threshold VDD Quiescent Supply Current tOFF_MIN IIN 170 213 316 461 200 2 4.5 0.7 0.693 2.47 1.78 0.7 2.5 1.8 1.7 194 243 352 516 300 25 1 2.5 1 2 4.25 50 1 5 219 273 389 571 450 40 5 5 2 10 4.40 ns A A mA A V mV A ns 28 5.5 5.5 0.707 2.53 1.82 ms V V V SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards ELECTRICAL CHARACTERISTICS (continued) (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER REFERENCE Reference Voltage Reference Load Regulation REF Undervoltage Lockout FAULT DETECTION OVP Trip Threshold (Referred to Nominal VOUT) UVP Trip Threshold (Referred to Nominal VOUT) POK1 Trip Threshold (Referred to Nominal VOUT) POK2 Trip Threshold (Referred to Nominal VVTTS and VVTTR) POK2 Disable Threshold (Measured at REFIN) UVP Blanking Time OVP, UVP, POK_ Propagation Delay POK_ Output Low Voltage POK_ Leakage Current ILIM Adjustment Range ILIM Input Leakage Current Current-Limit Threshold (Fixed) PGND1 to LX Current-Limit Threshold (Adjustable) PGND1 to LX Current-Limit Threshold (Fixed, Negative Direction) PGND1 to LX Current-Limit Threshold (Adjustable, Negative Direction) PGND1 to LX Zero-Crossing Detection Threshold PGND1 to LX Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis VILIM = 2V SKIP = AVDD 45 170 -75 50 200 -60 VILIM ISINK = 4mA VPOK_ = 5.5V, VFB = 0.8V, VVTTS = 1.3V 0.25 Lower level, falling edge, 1% hysteresis Upper level, rising edge, 1% hysteresis Lower level, falling edge, 1% hysteresis Upper level, rising edge, 1% hysteresis VREFIN rising (hysteresis = 75mV typ) From rising edge of SHDN UVP/OVP = AVDD (Note 4) 112 65 87 107 87.5 107.5 0.7 10 20 10 0.3 1 2.00 0.1 55 235 -45 116 70 90 110 90 110 120 75 93 113 92.5 % 112.5 0.9 40 V ms s V A V A mV mV mV % % % VREF AVDD = 4.5V to 5.5V; IREF = 0 IREF = 0 to 50A VREF rising Hysteresis 1.93 300 1.98 2 2.02 0.01 V V V mV SYMBOL CONDITIONS MIN TYP MAX UNITS MAX8550A SKIP = AVDD, VILIM = 2V -250 mV 3 +160 15 mV C C _______________________________________________________________________________________ 3 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A ELECTRICAL CHARACTERISTICS (continued) (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER MOSFET DRIVERS DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance in High State DL Gate-Driver On-Resistance in Low State Dead Time (Additional to Adaptive Delay) INPUTS AND OUTPUTS Logic Input Threshold (SHDN, STBY, SKIP) Logic Input Current (SHDN, STBY, SKIP) Dual-ModeTM Input Logic Levels (FB) Input Bias Current (FB) High Four-Level Input Logic Levels (TON, OVP/UVP) Floating REF Low Logic Input Current (TON, OVP/UVP) FB = GND OUT Input Resistance OUT Discharge-Mode On-Resistance DL Turn-On Level During Discharge Mode (Measured at OUT) 0.01 FB = AVDD FB adjustable mode -3 90 70 400 175 135 800 10 Low (2.5V output) High (1.8V output) 2.1 -0.1 AVDD 0.4 3.15 1.65 3.85 2.35 0.5 +3 350 270 1600 25 k A V +0.1 Rising edge Hysteresis -1 1.20 1.7 225 +1 0.05 2.20 V mV A V A DH falling to DL rising DL falling to DH rising VBST - VLX = 5V 1 1 0.5 30 30 4 4 3 ns SYMBOL CONDITIONS MIN TYP MAX UNITS 0.1 0.20 V Dual Mode is a trademark of Maxim Integrated Products, Inc. 4 _______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards ELECTRICAL CHARACTERISTICS (continued) (VIN = +15V, VDD = AVDD = V SHDN = STBY = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = TP0 = FB = SKIP = GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER VTTI Input Voltage Range VTTI Supply Current VTTI Shutdown Current REFIN Input Impedance REFIN Range VTT, VTTR UVLO Threshold (Measured at OUT) Soft-Start Charge Current VTT Internal MOSFET High-Side On-Resistance VTT Internal MOSFET Low-Side On-Resistance VTT Output Accuracy (Referred to VREFIN / 2) VTT Load Regulation VTT Current Limit VTTS Input Current VTTR Output Error (Referred to VREFIN / 2) VTTR Current Limit IVTTS ISS VSS = 0 IVTT = -100mA, VVTTI = 1.5V, AVDD = 4.5V IVTT = 100mA, AVDD = 4.5V VREFIN = 1.5V or 2.5V, IVTT = 1mA VREFIN = 2.5V, IVTT = 0 to 1.5A VREFIN = 1.5V, IVTT = 0 to 1A VTT = 0 or VTTI VVTTS = 1.5V, VTT open VREFIN = 1.5V or 2.5V, IVTTR = 0 VVTTR = 0 or VVTTI -1 18 32 3 -1 1 1 5 0.1 6.5 1 +1 50 VREFIN SYMBOL VVTTI IVTTI IVTT = IVTTR = 0 SHDN = GND VREFIN = 2.5V 12 1 0.01 0.1 4 0.3 0.3 +1 20 CONDITIONS MIN 1 <0.1 TYP MAX 2.8 1 10 30 2.8 0.20 UNITS V mA A k V V A % % A A % mA LINEAR REGULATORS (VTTR AND VTT) MAX8550A Note 1: Specifications to -40C are guaranteed by design, not production tested. Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-comparator threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation. Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds. _______________________________________________________________________________________ 5 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Typical Operating Characteristics (VVIN = 12V, VOUT = 2.5V, TON = GND, SKIP = AVDD, circuit of Figure 8, TA = +25C, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT (TON = GND) MAX8550A toc01 EFFICIENCY vs. LOAD CURRENT (TON = OPEN) MAX8550A toc02 SWITCHING FREQUENCY vs. LOAD CURRENT (TON = GND) 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 6 7 8 ILOAD (A) MAX8550A toc03 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 fSW = 600kHz VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V 100 90 80 EFFICIENCY (%) 70 60 50 40 30 VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V fSW = 300kHz SKIP = GND SKIP = AVDD 0.01 0.1 1 ILOAD (A) 10 100 20 10 0 0.01 0.1 1 ILOAD (A) SKIP = GND SKIP = AVDD 10 100 FREQUENCY (kHz) SKIP = GND SKIP = AVDD 9 10 11 12 SWITCHING FREQUENCY vs. INPUT VOLTAGE (TON = GND) 700 680 660 640 620 600 580 560 540 520 500 480 460 440 420 400 4 6 VIN (V) MAX8550A toc04 SWITCHING FREQUENCY vs. TEMPERATURE (TON = GND) MAX8550A oc05 OUTPUT VOLTAGE vs. LOAD CURRENT 2.535 2.530 2.525 VOUT (V) VIN = 15V, TON = GND MAX8550A toc06 700 690 680 FREQUENCY (kHz) 670 660 650 640 630 620 610 600 ILOAD = 12A 2.540 ILOAD = 12A FREQUENCY (kHz) 2.520 2.515 2.510 2.505 2.500 2.495 2.490 SKIP = GND SKIP = AVDD ILOAD = 0A 8 10 12 14 16 18 20 22 24 26 28 -40 -25 -10 5 20 35 50 65 80 0 2 4 6 8 10 12 14 TEMPERATURE (C) ILOAD (A) VTT VOLTAGE vs. VTT CURRENT MAX8550A toc07 VTTR VOLTAGE vs. VTTR CURRENT MAX8550A toc08 LINE REGULATION (VOUT vs. VIN) 2.54 2.53 2.52 VOUT (V) 2.51 2.50 2.49 2.48 2.47 2.46 2.45 ILOAD = 12A ILOAD = 0A MAX8550A toc09 1.28 1.27 1.26 1.28 1.27 1.26 VVTTR (V) 1.25 1.24 1.23 1.22 1.21 1.20 -15 -10 -5 0 IVTTR (mA) 5 10 2.55 VVTT (V) 1.25 1.24 1.23 1.22 1.21 1.20 -3 -2 -1 0 IVTT (A) 1 2 3 15 4 6 8 10 12 14 16 18 20 22 24 26 28 VIN (V) 6 _______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Typical Operating Characteristics (continued) (VVIN = 12V, VOUT = 2.5V, TON = GND, SKIP = AVDD, circuit of Figure 8, TA = +25C, unless otherwise noted.) LOAD TRANSIENT (BUCK) MAX8550A toc10 LOAD TRANSIENT VTT (-1.5A TO +1.5A) MAX8550A toc11 LOAD TRANSIENT VTT (-3A TO +3A) MAX8550A toc12 IVTT = 1.5A, IVTTR = 15mA ILOAD = 12A, IVTTR = 15mA VOUT 100mV/div VTT 100mV/div VTTR 100mV/div VOUT 50mV/div VTT 50mV/div ILOAD = 12A, IVTTR = 15mA VOUT 50mV/div VTT 50mV/div VTTR 50mV/div IVTT 2A/div VTTR 50mV/div IVTT 5A/div 40s/div 12A 0.1A 20s/div ILOAD 10A/div 0A 0A 40s/div POWER-UP WAVEFORMS MAX8550A toc13 POWER-DOWN WAVEFORMS MAX8550A toc14 STARTUP AND SHUTDOWN INTO HEAVY LOAD, DISCHARGE DISABLED MAX8550A toc15 VDD = 5V, ILOAD = 12A, IVTT = 1.5A, IVTTR = 15mA OUT 1V/div 0V VTT 2V/div 0V VTTR 1V/div VIN 10V/div 200s/div 0V VDD = 5V, ILOAD = 12A, IVTT = 1.5A, IVTTR = 15mA OUT 1V/div 0V VTT 2V/div 0V VTTR 1V/div 0V VIN 10V/div 200s/div ILOAD = 12A, IVTT = 1.5A VOUT 2V/div 0V VTT 1V/div 0V 0V POK1 5V/div SHDN 5V/div 1ms/div 0V 0V 0V STARTUP AND SHUTDOWN INTO LIGHT LOAD, DISCHARGE ENABLED MAX8550A toc16 STANDBY RESPONSE VTT LOADED AT 10 TO GND MAX8550A toc17a 10V/div 500mV/div 1.8V SHDN 5V/div 500mV/div 1.8V 0.9V STBY VOUT VTT VOUT 500mV/div 500mV/div 0.9V 0.9V VTT VTTR 500mV/div 0.9V VTTR 500mV/div 2ms/div 2ms/div _______________________________________________________________________________________ 7 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Typical Operating Characteristics (continued) (VVIN = 12V, VOUT = 2.5V, TON = GND, SKIP = AVDD, circuit of Figure 8, TA = +25C, unless otherwise noted.) STANDBY RESPONSE, VTT AT NO LOAD MAX8550A toc17b OVERVOLTAGE AND TURN-OFF OF BUCK OUTPUT MAX8550A toc18 0A 5V/div 500mV/div 500mV/div 1.8V 0.9V STBY VOUT VTT 0V IL 25A/div VOUT 2V/div 500mV/div 0.9V VTTR 0V DH 20V/div DL 5V/div 20s/div 0V 2ms/div SHORT CIRCUIT AND RECOVERY OF VDDQ MAX8550A toc19 SHORT CIRCUIT AND RECOVERY OF VDDQ MAX8550A toc20 SHORT CIRCUIT OF VTT MAX8550A toc21 UVP DISABLED, FOLDBACK CURRENT LIMIT VOUT 2V/div 0V ILOAD 10A/div UVP ENABLED VOUT 2V/div ILOAD 10A/div 0A VIN 10V/div 0V IVTT 5A/div VTT 1V/div 0V 0V 0A VIN 10V/div 0V IIN 2A/div 0A 400s/div IIN 2A/div 0A 400s/div 0A 400s/div 8 _______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards Pin Description PIN NAME FUNCTION On-Time Selection-Control Input. This four-level logic input sets the nominal DH on-time. Connect to GND, REF, AVDD, or leave TON unconnected to select the following nominal switching frequencies: TON = AVDD (200kHz) TON = OPEN (300kHz) TON = REF (450kHz) TON = GND (600kHz) Overvoltage/Undervoltage-Protection Control Input. This four-level logic input enables or disables the overvoltage and/or undervoltage protection. The overvoltage limit is 116% of the nominal output voltage. The undervoltage limit is 70% of the nominal output voltage. Discharge mode is enabled when OVP is also enabled. Connect the OVP/UVP pin to the following pins for the desired function: OVP/UVP = AVDD (Enable OVP and discharge mode, enable UVP.) OVP/UVP = OPEN (Enable OVP and discharge mode, disable UVP.) OVP/UVP = REF (Disable OVP and discharge mode, enable UVP.) OVP/UVP = GND (Disable OVP and discharge mode, disable UVP.) +2.0V Reference Voltage Output. Bypass to GND with a 0.1F (min) capacitor. REF can supply 50A for external loads. Can be used for setting voltage for ILIM. REF turns off when SHDN is low and OUT < 0.1V. Valley Current-Limit Threshold Adjustment for Buck Regulator. The current-limit threshold across PGND and LX is 0.1 times the voltage at ILIM. Connect ILIM to a resistive divider, typically from REF to GND, to set the current-limit threshold between 25mV and 200mV. This corresponds to a 0.25V to 2V range at ILIM. Connect ILIM to AVDD to select the 50mV default current-limit threshold. See the Setting the Current Limit section. Buck Power-Good Open-Drain Output. POK1 is low when the buck output voltage is more than 10% above or below the normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start circuit has terminated. POK1 is low in shutdown. LDO Power-Good Open-Drain Output. In normal mode, POK2 is low when either VTTR or VTTS is more than 10% above or below the normal regulation point, which is typically REFIN / 2. In standby mode, POK2 responds only to the VTTR input. POK2 is low in shutdown, and when VREFIN is less than 0.8V. Standby. Connect to GND for low-quiescent mode where the VTT output is open circuit. POK2 takes input from only VTTR in this mode. PWM output can be on or off, depending on the state of SHDN. Soft-Start Control for VTT. Connect a capacitor (C9 in the Typical Applications Circuit) from SS to ground (see the Soft-Start Capacitor Selection section). Leave SS open to disable soft-start. SS discharges to ground when VTT is off. See the POR, UVLO, and Soft-Start section. Sensing Pin for Termination Supply Output. Normally connected to VTT pin to allow accurate regulation to half the REFIN voltage. Connected to a resistive divider from VTT to GND to regulate VTT to higher than half the REFIN voltage. Termination Reference Voltage. VTTR tracks VREFIN / 2. MAX8550A 1 TON 2 OVP/ UVP 3 REF 4 ILIM 5 POK1 6 POK2 7 STBY 8 SS 9 10 VTTS VTTR _______________________________________________________________________________________ 9 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Pin Description (continued) PIN 11 12 13 14 15 NAME PGND2 VTT VTTI REFIN FB FUNCTION Power Ground for VTT and VTTR. Connect PGND2 externally to the underside of the exposed pad. Termination Power-Supply Output. Connect VTT to VTTS to regulate to VREFIN / 2. Power-Supply Input Voltage for VTT and VTTR. Normally connected to the output of the buck regulator for DDR application. External Reference Input. This is used to regulate the VTT and VTTR outputs to VREFIN / 2. Feedback Input for Buck Output. Connect to AVDD for a +1.8V fixed output or to GND for a +2.5V fixed output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output voltage. FB regulates to +0.7V. Output-Voltage Sense Connection. Connect to the positive terminal of the buck output filter capacitor. OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the Typical Applications Circuit). OUT also serves as the buck output's feedback input in fixed-output modes. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10 resistor connected between OUT and GND. OUT also acts as the input to the VTT and VTTR UVLO detector. Input-Voltage Sense Connection. Connect to input power source. VIN is used only to set the PWM's ontime one-shot timer. IN voltage range is from 2V to 28V. High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO. External Inductor Connection. Connect LX to the input side of the inductor. LX is used for both current limit and the return supply of the DH driver. Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the Typical Applications Circuit (Figure 8). See the Boost-Supply Diode and Capacitor Selection section. Synchronous-Rectifier Gate-Driver Output. Swings from PGND to VDD. Supply Input for the DL Gate Drive. Connect to the +4.5V to +5.5V system supply voltage. Bypass to PGND1 with a 1F (min) ceramic capacitor. Power Ground for Buck Controller. Connect PGND1 externally to the underside of the exposed pad. Analog Ground for Both Buck and LDO. Connect GND externally to the underside of the exposed pad. Pulse-Skipping Control Input. Connect to AVDD for low-noise, forced-PWM mode. Connect to GND to enable pulse-skipping operation. Analog Supply Input for Both Buck and LDO. Connect to the +4.5V to +5.5V system supply voltage with a series 10 resistor. Bypass to GND with a 1F or greater ceramic capacitor. Shutdown Control Input. Use to control buck output. A rising edge on SHDN clears the overvoltageand undervoltage-protection fault latches (see Tables 2 and 3). Connect to AVDD for normal operation. This is a test pin. Must connect to GND externally. 16 OUT 17 18 19 20 21 22 23 24 25 26 27 28 VIN DH LX BST DL VDD PGND1 GND SKIP AVDD SHDN TP0 10 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A IN tOFF TRIG Q TON ON-TIME COMPUTE OUT ONE-SHOT MAX8550A BST tON TRIG ONE-SHOT Q R LX S Q DH VDD DL S INTREF 1.16 x INTREF R Q PGND OVP/UVP QUAD LEVEL DECODE BUCK ON/OFF ILIM OVP/UVP LATCH SHDN 1.0V LX VDD - 1V TP0 SHUTDOWN DECODER BIAS ON/OFF SKIP 20ms TIMER STBY 0.7 x INTREF VTT ON/OFF VTTR ON/OFF INTREF + 10% INTREF - 10% VOUT = 2.5V POK1 VOUT = 1.8V ZERO CROSSING LX OUT DISCHARGE LOGIC N AVDD 2V REFERENCE FB DECODE GND N REF FB INTREF VTTS 10k 0.1V REFIN / 2 - 10% REFIN / 2 + 10% OUT REFIN / 2 VDD VTTI N VTT N VTT ILIM VTTI PGND2 VTTR 10k REFIN POK2 VDD POWER-DOWN N CURRENT LIMITS PGND2 REFIN / 2 - 10% REFIN / 2 + 10% SS Figure 1. Functional Diagram ______________________________________________________________________________________ 11 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Detailed Description The MAX8550A combines a synchronous-buck PWM controller, an LDO linear regulator, and a 10mA reference output buffer. The buck controller drives two external n-channel MOSFETs to deliver load currents up to 12A and generate voltages down to 0.7V from a +2V to +28V input. The LDO linear regulator can sink and source up to 1.5A continuous and 3A peak current with relatively fast response. These features make the MAX8550/MAX8551 ideally suited for DDR memory applications. The MAX8550A buck regulator is equipped with a fixed switching frequency of up to 600kHz using Maxim's proprietary constant on-time Quick-PWM architecture. This control scheme handles wide input/output voltage ratios with ease, and provides 100ns "instant-on" response to load transients, while maintaining high efficiency with relatively constant switching frequency. The buck controller, LDO, and a reference output buffer are provided with independent current limits. Lossless foldback current limit in the buck regulator is achieved by monitoring the drain-to-source voltage drop of the low-side FET. The ILIM input is used to adjust this current limit. Overvoltage protection, if selected, is achieved by latching the low-side synchronous FET on and the high-side FET off when the output voltage is over 116% of its set output. It also features an optional undervoltage protection by latching the MOSFET drivers to the OFF state during an overcurrent condition, when the output voltage is lower than 70% of the regulated output. This helps minimize power dissipation during a short-circuit condition. The current limit in the LDO and buffered reference output buffer is 5A and 32mA, respectively, and neither have the over- or undervoltage protection. When the current limit in either output is reached, the output no longer regulates the voltage, but regulates the current to the value of the current limit. the IC. The current from the AVDD and V DD power supply must supply the current for the IC and the gate drive for the MOSFETs. This maximum current can be estimated as: IBIAS = IVDD + IAVDD + fSW x (QG1 + QG2 ) where IVDD + IAVDD are the quiescent supply currents into VDD and AVDD, QG1 and QG2 are the total gate charges of MOSFETs Q1 and Q2 (at VGS = 5V) in the Typical Applications Circuit, and fSW is the switching frequency. Free-Running Constant-On-Time PWM The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode regulator with voltage feed-forward (Figure 1). This architecture relies on the output filter capacitor's ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to the output voltage. Another one-shot sets a minimum off-time of 300ns (typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. On-Time One-Shot (TON) The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to input and output voltages. The high-side switch on-time is inversely proportional to the input voltage (VIN) and is proportional to the output voltage: t ON = K x (VOUT + ILOAD x RDS(ON)Q2 VIN ) +5V Bias Supply (VDD and AVDD) The MAX8550A requires an external +5V bias supply in addition to the input voltage (VIN). Keeping the bias supply external to the IC improves the efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and the gate drivers. If stand-alone capability is needed, then the +5V supply can be generated with an external linear regulator such as the MAX1615. VDD, AVDD, and IN can be connected together if the input source is a fixed +4.5V to +5.5V supply. VDD is the supply input for the buck regulator's MOSFET drivers, and AVDD supplies the power for the rest of 12 where K (the switching period) is set by the TON input connection (Table 1) and RDS(ON)Q2 is the on-resistance of the synchronous rectifier (Q2) in the Typical Applications Circuit (Figure 8). This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: 1) The frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band. 2) The inductor ripple-current operating point remains relatively constant, resulting in an easy design methodology and predictable output voltage ripple. ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics table (approximately 12.5% at 600kHz and 450kHz, and 10% at 200kHz and 300kHz). On-times at operating points far removed from the conditions specified in the Electrical Characteristics table can vary over a wider range. For example, the 600kHz setting typically runs approximately 10% slower with inputs much greater than 5V due to the very short on-times required. The constant on-time translates only roughly to a constant switching frequency. The on-times guaranteed in the Electrical Characteristics table are influenced by resistive losses and by switching delays in the highside MOSFET. Resistive losses, which include the inductor, both MOSFETs, the output capacitor's ESR, and any PC board copper losses in the output and ground, tend to raise the switching frequency as the load increases. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times are added to the effective ontime. The dead time occurs only in PWM mode (SKIP = VDD) and during dynamic output-voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: fSW = VOUT + VDROP1 t ON (VIN + VDROP2 ) for the default 50mV current-limit threshold), the comparator forces DL low (Figure 1). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half the peak-to-peak ripple current, which is a function of the inductor value (Figure 2). This threshold is relatively constant, with only a minor dependence on the input voltage (VIN): x K VIN - VOUT V ILOAD(SKIP) = OUT VIN 2L where K is the on-time scale factor (see Table 1). For example, in the Typical Applications Circuit of Figure 8 (K = 1.7s, VOUT = 2.5V, VIN = 12V, and L = 1H), the pulse-skipping switchover occurs at: 2.5V x 1.7s 12V - 2.5V = 1.68A 2 x 1H 12V The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resis- MAX8550A where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including the synchronous rectifier, the inductor, and any PC board resistances; VDROP2 is the sum of the resistances in the charging path, including the high-side switch (Q1 in the Typical Applications Circuit), the inductor, and any PC board resistances, and tON is the one-shot on-time (see the On-Time One-Shot (TON) section. Table 1. Approximate K-Factor Errors TYPICAL K-FACTOR KERROR FACTOR (%) (s) MINIMUM VIN AT VOUT = 2.5V (h = 1.5; SEE THE DROPOUT PERFORMANCE SECTION) 3.15 3.47 4.13 5.61 TON SETTING Automatic Pulse-Skipping Mode (SKIP = GND) In skip mode (SKIP = GND), an inherent automatic switchover to PFM takes place at light loads (Figure 2). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator differentially senses the inductor current across the synchronous-rectifier MOSFET (Q2 in the Typical Applications Circuit, Figure 8). Once V PGND - V LX drops below 5% of the current-limit threshold (2.5mV 200 (TON = AVDD) 300 (TON = OPEN) 450 (TON = REF) 600 (TON = GND) 5.0 3.3 2.2 1.7 10 10 12.5 12.5 ______________________________________________________________________________________ 13 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards tance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input-voltage levels. DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX8550A regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction (SKIP = GND and ILOAD < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. tion circuit, this current-limit method is effective in almost every circumstance. In forced-PWM mode, the MAX8550A also implements a negative current limit to prevent excessive reverse inductor currents when the buck regulator output is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when VILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM. A 2A to 20A divider current is recommended for accuracy and noise immunity. The current-limit threshold adjustment range is from 25mV to 200mV. In the adjustable mode, the currentlimit threshold voltage (from PGND1 to LX) is precisely 1/10th the voltage seen at ILIM. The threshold defaults to 50mV when ILIM is connected to AVDD. The logic threshold for switchover to the 50mV default value is approximately AVDD - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen between LX and GND. MAX8550A Forced-PWM Mode (SKIP = AVDD) The low-noise forced-PWM mode (SKIP = AVDD) disables the zero-crossing comparator, which controls the low-side switch on-time. This forces the low-side gatedrive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while DH maintains a duty factor of VOUT / VIN. Forced-PWM mode keeps the switching frequency fairly constant. However, forced-PWM operation comes at a cost where the no-load VDD bias current remains between 2mA and 20mA due to the external MOSFET's gate charge and switching frequency. Forced-PWM mode is most useful for reducing audio frequency noise, improving load-transient response, and providing sink-current capability for dynamic output-voltage adjustment. POR, UVLO, and Soft-Start Internal power-on reset (POR) occurs when AVDD rises above approximately 2V, resetting the fault latch and the soft-start counter, powering up the reference, and preparing the buck regulator for operation. Until AVDD reaches 4.25V (typ), AV DD undervoltage-lockout Current-Limit Buck Regulator (ILIM) Valley Current Limit The current-limit circuit for the buck regulator portion of the MAX8550A employs a unique "valley" current-sensing algorithm that senses the voltage drop across LX and PGND1 and uses the on-resistance of the rectifying MOSFET (Q2 in the Typical Applications Circuit, Figure 8) as the current-sensing element. If the magnitude of the current-sense signal is above the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle (Figure 4). With valley current-limit sensing, the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor current ripple. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and input voltage. When combined with the undervoltage-protec- V -V I = IN OUT L t IPEAK INDUCTOR CURRENT ILOAD = IPEAK / 2 0 ON-TIME TIME Figure 2. Pulse-Skipping/Discontinuous Crossover Point 14 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A MAX8550A TO PWM CONTROLLER (SEE FIGURE 1) REF RA ILIM CREF CILIM RB 1.0V LX VDD - 1V Figure 3. Adjustable Current-Limit Threshold IPEAK ILOAD ILOAD(MAX) ILIM(VAL) = 1 - LIR 2 ILIMIT ( )xI LOAD The buck regulator's internal soft-start allows a gradual increase of the current-limit level during startup to reduce the input surge currents. The MAX8550A divides the soft-start period into five phases. During the first phase, the controller limits the current limit to only 20% of the full current limit. If the output does not reach regulation within 425s, soft-start enters the second phase, and the current limit is increased by another 20%. This process repeats until the maximum current limit is reached, after 1.7ms, or when the output reaches the nominal regulation voltage, whichever occurs first. Adding a capacitor in parallel with the external ILIM resistors creates a continuously adjustable analog soft-start function for the buck regulator's output. Soft-start in the LDO section can be realized by connecting a capacitor between the SS pin and ground. When VTT is turned off or placed in standby mode, or during thermal shutdown of the LDOs, the SS capacitor is discharged. When VTT is turned on or when the thermal limit is removed, an internal 4A (typ) current charges the SS capacitor. The resulting ramp voltage on SS linearly increases the current-limit comparator threshold to the VTT output, until full current limit is attained when SS reaches approximately 1.6V. This lowering of the current limit during startup limits the initial inrush current peaks, particularly when driving capacitors. Choose the value of the SS cap appropriately to set the soft-start time window. Leave SS floating to disable the soft-start feature. INDUCTOR CURRENT 0 TIME Figure 4. Valley Current-Limit Threshold (UVLO) circuitry inhibits switching. The controller inhibits switching by pulling DH low and holding DL low when OVP and shutdown discharge are disabled (OVP/UVP = REF or GND) or forcing DL high when OVP and shutdown discharge are enabled (OVP/UVP = AVDD or OPEN). See Table 3 for a detailed truth table for OVP/UVP and shutdown settings. When AVDD rises above 4.25V, the controller activates the buck regulator and initializes the internal soft-start. ______________________________________________________________________________________ 15 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Power-OK (POK1) POK1 is an open-drain output for a window comparator that continuously monitors VOUT. POK1 is actively held low when SHDN is low and during the buck regulator output's soft-start. After the digital soft-start terminates, POK1 becomes high impedance as long as the output voltage is within 10% of the nominal regulation voltage set by FB. When VOUT drops 10% below or rises 10% above the nominal regulation voltage, the MAX8550A pulls POK1 low. Any fault condition forces POK1 low until the fault latch is cleared by toggling SHDN or cycling AVDD power below 1V. For logic-level output voltages, connect an external pullup resistor between POK1 and AVDD. A 100k resistor works well in most applications. Note that the POK1 window detector is completely independent of the overvoltage- and undervoltage-protection fault detectors and the state of VTTS and VTTR. by the load current and its output capacitance. The buck regulator detects and latches the discharge-mode state set by the OVP/UVP setting on startup. When OUT is discharging, both VTT and VTTR outputs will remain alive and continue to track REFIN until OUT drops to 0.1V. STBY The STBY input is an active-low input that is used to shut down only the VTT output. When STBY is low, VTT is high impedance. Power-OK (POK2) POK2 is the open-drain output for a window comparator that continuously monitors the VTTS input and VTTR output. POK2 is pulled low when REFIN is less than 0.8V. POK2 is high impedance as long as the output voltage is within 10% of the nominal regulation voltage as set by REFIN. When V VTTS or V VTTR rises 10% above or 10% below its nominal regulation voltage, the MAX8550A pulls POK2 low. For logic-level output voltages, connect an external pullup resistor between POK2 and AVDD. A 100k resistor works well in most applications. SHDN and Output Discharge The SHDN input corresponds to the buck regulator and places the buck regulator's portion of the IC in a lowpower mode (see the Electrical Characteristics table). SHDN is also used to reset a fault signal such as an overvoltage or undervoltage fault. When output discharge is enabled, (OVP/UVP = AVDD or open) and SHDN is pulled low, or if UVP is enabled (OVP/UVP = AVDD) and VOUT falls to 70% of its regulation set point, the MAX8550A discharges the buck regulator output (through the OUT input) through an internal 10 switch to ground. While the output is discharging, DL is forced low and the PWM controller is disabled but the reference remains active to provide an accurate threshold. Once the output voltage drops below 0.1V, the MAX8550A shuts down the reference and pulls DL high, effectively clamping the buck output and LX to ground. When output discharge is disabled (OVP/UVP = REF or GND), the controller does not actively discharge the buck output and the DL driver remains low. Under these conditions, the buck output discharge rate is determined Current Limit (LDO for VTT and VTTR Buffer) The VTT output is a linear regulator that regulates the input (VTTI) to half the VREFIN voltage. The feedback point for VTT is at the VTTS input (Figure 1). VTT is capable of sinking and sourcing at least 1.5A of continuous current and 3A peak current. The current limit for VTT and VTTR is typically 5A and 32mA, respectively. When the current limit for either output is reached, the outputs regulate the current, not the voltage. Fault Protection The MAX8550A provides overvoltage/undervoltage fault protection in the buck controller. Select OVP/UVP to enable and disable fault protection as shown in Table 3. Once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. Table 2. Shutdown and Standby Control Logic SHDN AVDD* AVDD** GND*** STBY AVDD* GND** X BUCK OUTPUT (VDDQ) ON ON OFF VTT ON OFF (high impedance) OFF (tracking 1/2 REFIN) VTTR ON ON OFF (tracking 1/2 REFIN) *For DDR application, this is referred as S0 state, where all outputs are on. **For DDR application, this is referred as S3 state, where VDDQ and VTTR are kept on, but VTT is turned off (high impedance). ***For DDR application, this is referred as S4/S5 states, where all outputs are off. Discharge mode should be selected (OVP/UVP = AVDD or OPEN, see Table 3) to discharge the outputs. 16 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards Overvoltage Protection (OVP) When the output voltage rises above 116% of the nominal regulation voltage and OVP is enabled (OVP/UVP = AVDD or open), the OVP circuit sets the fault latch, shuts down the PWM controller, and immediately pulls DH low and forces DL high. This turns on the synchronous-rectifier MOSFET (Q2 in the Typical Applications Circuit of Figure 8) with a 100% duty cycle, rapidly discharging the output capacitor and clamping the output to ground. Note that immediately latching DL high can cause the output voltage to go slightly negative due to energy stored in the output LC circuit at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse-polarity clamp. Toggle SHDN or cycle AVDD below 1V to clear the fault latch and restart the controller. OVP is disabled when OVP/UVP is connected to REF or GND (see Table 3). OVP only applies to the buck output. The VTT and VTTR outputs do not have overvoltage protection. Undervoltage Protection (UVP) When the output voltage drops below 70% of its regulation voltage while UVP is enabled, the controller sets the fault latch and begins the discharge mode (see the Shutdown and Output Discharge section). When the output voltage drops to 0.1V, the synchronous rectifier (Q2 in the Typical Applications Circuit) turns on and clamps the buck output to GND. UVP is ignored for at least 10ms (min) after startup or after a rising edge on SHDN. Toggle SHDN or cycle AVDD power below 1V to clear the fault latch and restart the controller. UVP is disabled when OVP/UVP is left open or connected to GND (see Table 3). UVP only applies to the buck output. The VTT and VTTR outputs do not have undervoltage protection. Thermal Fault Protection The MAX8550A features two thermal-fault-protection circuits. One monitors the buck-regulator portion of the IC and the other monitors the linear regulator (VTT) and the reference buffer output (VTTR). When the junction temperature of the buck-regulator portion of the MAX8550A rises above +160C, a thermal sensor activates the fault latch, pulls POK1 low, and shuts down the buck-controller output using discharge mode regardless of the OVP/UVP setting. Toggle SHDN or cycle AVDD below 1V to reactivate the controller after the junction temperature cools by 15C. If the VTT and VTTR regulator portion of the IC has its die temperature rise above +160C, then VTT and VTTR shut off, go high impedance, and restart after the die portion of the IC cools by 15C. Both thermal faults are independent. For example, if the VTT output is overloaded to the point that it triggers its thermal fault, the buck regulator continues to function. MAX8550A Design Procedure Firmly establish the input voltage range (VIN) and maximum load current (ILOAD) in the buck regulator before choosing a switching frequency and inductor operating point (ripple current ratio or LIR). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: * Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case voltage. The minimum value (VIN(MIN)) must account for the lowest voltage after drops due to connectors and fuses. If there is a choice, lower input voltages result in better efficiency. Table 3. OVP/UVP Fault Protection OVP/UVP AVDD DISCHARGE Yes. DL forced high when SHDN is low and OUT < 0.1V. Yes. DL forced high when SHDN is low and OUT < 0.1V. No. DL forced low when SHDN is low. No. DL forced low when SHDN is low. UVP PROTECTION Enabled OVP PROTECTION Enabled OPEN Disabled Enabled REF GND Enabled Disabled Disabled Disabled ______________________________________________________________________________________ 17 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards * Maximum Load Current. There are two values to consider. The peak load current (IPEAK) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. * Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses proportional to frequency and VIN2. The optimum frequency is also a moving target due to rapid improvements in MOSFET technology that are making higher frequencies more practical. * Inductor Operating Point. This choice provides tradeoffs: size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP = low at light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. MAX8550A where VFB is 0.7V, RC and RD are shown in Figure 6, and VRIPPLE is: VRIPPLE = LIR x ILOAD(MAX) x RESR Setting the VTT and VTTR Voltages (LDO) The termination power-supply output (VTT) can be set by two different methods. First, the VTT output can be connected directly to the VTTS input to force VTT to regulate to VREFIN / 2. Secondly, VTT can be forced to regulate higher than VREFIN / 2 by connecting a resistive divider from VTT to VTTS. The maximum value for VTT is VVTTI VDROPOUT where VDROPOUT = IVTT x 0.3 (max) at TA = +85C. The termination reference voltage (VTTR) tracks 1/2 VREFIN. Inductor Selection (Buck) The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT (VIN - VOUT ) VIN x fSW x ILOAD(MAX) x LIR For example: ILOAD(MAX) = 12A, VIN = 12V, VOUT = 2.5V, fSW = 600kHz, 30% ripple current or LIR = 0.3: L= 2.5V (12V - 2.5V) 1H 12V x 600kHz x 12A x 0.3 Setting the Output Voltage (Buck) Preset Output Voltages The MAX8550A dual-mode operation allows the selection of common voltages without requiring external components (Figure 5). Connect FB to GND for a fixed 2.5V output, to AVDD for a fixed 1.8V output, or connect FB directly to OUT for a fixed 0.7V output. Setting the Buck Regulator Output (VOUT) with a Resistive Voltage-Divider at FB The buck-regulator output voltage can be adjusted from 0.7V to 5.5V using a resistive voltage-divider (Figure 6). The MAX8550A regulates FB to a fixed reference voltage (0.7V). The adjusted output voltage is: R V VOUT = VFB 1 + C + RIPPLE 2 RD TO ERROR AMPLIFIER FB MAX8550A OUT 1.8V (FIXED) REF (2.0V) 2.5V (FIXED) 0.1V Figure 5. Dual-Mode Feedback Decoder 18 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards L LX VOUT tem, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10C temperature rise at the RMS input current for optimal reliability and lifetime. COUT MAX8550A MAX8550A DL PGND1 GND OUT Q2 Output Capacitor Selection (Buck) The output filter capacitor must have low enough equivalent series resistance (RESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. For processor core voltage converters and other applications in which the output is subject to violent load transients, the output capacitor's size depends on how much RESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VSTEP ILOAD(MAX) RC FB RD Figure 6. Setting VOUT with a Resistive Voltage-Divider Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at frequencies up to 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) 1 + 2 Most inductor manufacturers provide inductors in standard values, such as 1.0H, 1.5H, 2.2H, 3.3H, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. In applications without large and fast load transients, the output capacitor's size often depends on how much RESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller is approximately equal to the total inductor ripple current multiplied by the output capacitor's RESR. Therefore, the maximum RESR required to meet ripple specifications is: RESR VRIPPLE ILOAD(MAX) x LIR Input Capacitor Selection (Buck) The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents: IRMS = ILOAD VOUT (VIN - VOUT ) VIN IRMS has a maximum value of ILOAD / 2 when VIN = 2 x VOUT. For most applications, nontantalum capacitors (ceramic, aluminum, POS, or OSCON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX8550A is operated as the second stage of a two-stage power conversion sys- The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OSCONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that can affect the overall stability (see the Stability Requirements section). ______________________________________________________________________________________ 19 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Stability Requirements For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR SW where : fESR = 1 2 x RESR x COUT VTT Output Capacitor Selection (LDO) A minimum value of 60F is needed to stabilize the VTT output for load currents up to 1.5A. This value of capacitance limits the regulator's unity-gain bandwidth frequency to about 700kHz (typ) to allow adequate phase margin for stability. To keep the capacitor acting as a capacitor within the regulator's bandwidth, it is important that ceramic caps with low ESR and ESL be used. Since the gain bandwidth is also determined by the transconductance of the output FETs, which increases with load current, the output capacitor needs to be greater than 60F if the load current exceeds 1.5A, but can be smaller than 60F if the maximum load current is less than 1.5A. As a rule, choose the minimum capacitance and maximum ESR for the output capacitor using the following: COUT _ MIN = 60F x RESR _ MAX = 5m x ILOAD 1.5A 1.5A ILOAD If COUT consists of multiple same-value capacitors, as in the Typical Applications Circuit of Figure 8, the fESR remains the same as that of a single capacitor. For a typical 600kHz application, the ESR zero frequency must be well below 190kHz, preferably below 100kHz. Two 150F/4V Sanyo POS capacitors are used to provide 12m (max) of RESR. This results in a zero at 42kHz, well within the bounds of stability. Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. 20 RESR value is measured at the unity-gain-bandwidth frequency given by approximately: fGBW = 40 COUT x ILOAD 1.5A Once these conditions for stability are met, additional capacitors, including those of electrolytic and tantalum types, can be connected in parallel to the ceramic capacitor (if desired) to further suppress noise or voltage ripple at the output. VTTR Output Capacitor Selection (LDO) The VTTR buffer is a scaled-down version of the VTT regulator, with much smaller output transconductance. Its compensation cap can therefore be smaller, and its ESR larger, than what is required for its larger counterpart. For typical applications requiring load current up to 15mA, a ceramic cap with a minimum value of 1F is recommended (R ESR < 0.3). Connect this cap between VTTR and the analog ground plane. VTTI Input Capacitor Selection (LDO) Both the VTT and VTTR output stages are powered from the same VTTI input. Their output voltages are referenced to the same REFIN input. The value of the VTTI bypass capacitor is chosen to limit the amount of ripple/noise at VTTI, or the amount of voltage dip during a load transient. Typically VTTI is connected to the output of the buck regulator, which already has a large bulk ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards capacitor. Nevertheless, a ceramic capacitor of at least 10F must be used and must be added and placed as close as possible to the VTTI pin. This value must be increased with larger load current, or if the trace from the VTTI pin to the power source is long and has significant impedance. Furthermore, to prevent undesirable VTTI bounce from coupling back to the REFIN input and possibly causing instability in the loop, the REFIN pin should ideally tap its signal from a separate lowimpedance DC source rather than directly from the VTTI input. If the latter is unavoidable, increase the amount of bypass capacitance at the VTTI input and add additional bypass at the REFIN pin. Use RDS(ON) at TJ(MAX): PLSDC = 2ILOAD x VF x t DT x fSW where VF is the body-diode forward-voltage drop, tDT is the dead time (30ns), and fSW is the switching frequency. Because of the zero-voltage switch operation, the low-side MOSFET gate-drive loss occurs as a result of charging and discharging the input capacitance, (CISS). This loss is distributed among the average DL gate-driver's pullup and pulldown resistance, RDL (1), and the internal gate resistance (RGATE) of the MOSFET (2). The drive power dissipated is given by: PLSDR = CISS x VGS2 x fSW x RGATE RGATE + RDL MAX8550A MOSFET Selection (Buck) The MAX8550A drives external, logic-level, n-channel MOSFETs as the circuit-switch elements. The key selection parameters: On-resistance (RDS(ON)): the lower, the better. Maximum drain-to-source voltage (VDSS): should be at least 20% higher than input supply rail at the highside MOSFET's drain. Gate charges (QG, QGD, QGS): the lower the better. Choose MOSFETs with rated RDS(ON) at VGS = 4.5V. For a good compromise between efficiency and cost, choose the high-side MOSFET that has a conduction loss equal to its switching loss at nominal input voltage and maximum output current (see below). For the lowside MOSFET, make sure that it does not spuriously turn on because of dV/dt caused by the high-side MOSFET turning on, as this results in shoot-through current degrading efficiency. MOSFETs with a lower QGD to QGS ratio have higher immunity to dV/dt. For proper thermal-management design, calculate the power dissipation at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage. For the low-side MOSFET, the worst case is at VIN(MAX). For the high-side MOSFET, the worst case could be at either VIN(MIN) or VIN(MAX). The high-side MOSFET and low-side MOSFET have different loss components due to the circuit operation. The low-side MOSFET operates as a zero-voltage switch; therefore, major losses are: * The channel-conduction loss (PLSCC) * The body-diode conduction loss (PLSDC) * The gate-drive loss (PLSDR): V PLSCC = 1 - OUT x ILOAD2 x RDS(ON) VIN The high-side MOSFET operates as a duty-cycle control switch and has the following major losses: * The channel-conduction loss (PHSCC) * The VI overlapping switching loss (PHSSW) * The drive loss (PHSDR) (The high-side MOSFET does not have body-diode conduction loss because the diode never conducts current): PHSCC = VOUT x ILOAD2 x RDS(ON) VIN Use RDS(ON) at TJ(MAX): PHSSW = VIN x ILOAD x fSW x QGS + QGD IGATE where IGATE is the average DH-driver output current determined by: IGATE(ON) = 2.5V RDH + RGATE where RDH is the high-side MOSFET driver's on-resistance (1 typ) and RGATE is the internal gate resistance of the MOSFET (2): PHSDR = QG x VGS x fSW x RGATE RGATE + RDH ______________________________________________________________________________________ 21 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards where VGS = VDD = 5V. In addition to the losses above, allow about 20% more for additional losses because of MOSFET output capacitances and low-side MOSFET body-diode reverse-recovery charge dissipated in the high-side MOSFET that is not well defined in the MOSFET data sheet. Refer to the MOSFET data sheet for thermal-resistance specifications to calculate the PC board area needed to maintain the desired maximum operating junction temperature with the above-calculated power dissipations. To reduce EMI caused by switching noise, add a 0.1F ceramic capacitor from the high-side switch drain to the low-side switch source, or add resistors in series with DH and DL to slow down the switching transitions. Adding series resistors increases the power dissipation of the MOSFET, so ensure that this does not overheat the MOSFET. MAX8550A The power loss of the snubber circuit (PRSNUB) is dissipated in the resistor and can be calculated as: PRSNUB = CSNUB x VIN2 x fSW where VIN is the input voltage and fSW is the switching frequency. Choose an RSNUB power rating that meets the specific application's derating rule for the power dissipation calculated. Setting the Current Limit (Buck) The current-sense method used in the MAX8550/ MAX8551 makes use of the on-resistance (RDS(ON)) of the low-side MOSFET (Q2 in the Typical Applications Circuit). When calculating the current limit, use the worstcase maximum value for RDS(ON) from the MOSFET data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each 1C of temperature rise. The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ILOAD(MAX) x LIR ILIM (VAL) > ILOAD(MAX) - 2 where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the on-resistance of Q2 (RDS(ON)Q2). For the 50mV default setting, connect ILIM to AVDD. In adjustable mode, the valley current-limit threshold is precisely 1/10th* the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to GND with ILIM connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10A to prevent significant inaccuracy in the valley current-limit tolerance. Foldback Current Limit Alternately, foldback current limit can be implemented if the UVP latch option is not available. Foldback current limit reduces the power dissipation of external components so they can withstand indefinite overload and short circuit, with automatic recovery after the overload or short circuit is removed. To implement foldback current limit, connect a resistor from VOUT to ILIM (R6 in Figure 7 and the Typical Applications Circuit), in addition to the resistor-divider network (R4 and R5) *In the negative direction, the adjustable current limit is typically -1/8th the voltage seen at ILIM. MOSFET Snubber Circuit (Buck) Fast switching transitions cause ringing because of a resonating circuit formed by the parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at LX's rising and falling transitions and can interfere with circuit performance and generate EMI. To dampen this ringing, an optional series RC snubber circuit is added across each switch. Below is a simple procedure for selecting the value of the series RC of the snubber circuit: 1) Connect a scope probe to measure VLX to PGND1, and observe the ringing frequency, fR. 2) Estimate the circuit parasitic capacitance (CPAR) at LX by first finding a capacitor value, which, when connected from LX to PGND1, reduces the ringing frequency by half. CPAR can then be calculated as 1/3rd the value of the capacitor value found. 3) Estimate the circuit parasitic inductance (LPAR) from the equation: LPAR = 1 2 (2 x fR ) x CPAR 4) Calculate the resistor for critical dampening (RSNUB) from the equation: RSNUB = 2 x fR x LPAR. Adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. 5) The capacitor (C SNUB) should be at least 2 to 4 times the value of CPAR to be effective. 22 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards used for setting the adjustable current limit as shown in Figure 7. The following is a procedure for calculating the value of R4, R5, and R6: 1) Calculate the voltage, VILIM(NOM), required at ILIM when the output voltage is at nominal: LIR VILIM (NOM ) = 10 x ILOAD(MAX) x 1 2 x RDS(ON)Q2 2) Pick a percentage of foldback, PFB, from 15% to 40%. 3) Calculate the voltage, VILIM(0V), when the output is shorted (0V): VILIM(0V) = PFB x VILIM(NOM) 4) The value for R4 can be calculated as: R4 = 2V - VILIM(0V) 10A 6) Then R6 can be calculated as: R6 = VOUT x R4 x R56 V - VILIM(NOM) - VILIM(0V) x R4 - OUT VILIM(NOM) - VILIM(0V) x R56 MAX8550A ( (( ( )) ) ) 7) Then R5 is calculated as: R5 = R6 x R56 R6 - R56 Boost-Supply Diode and Capacitor Selection (Buck) A low-current Schottky diode, such as the CMDSH-3 from Central Semiconductor, works well for most applications. Do not use large-power diodes, because higher junction capacitance can charge up the voltage at BST to the LX voltage and this exceeds the absolute maximum rating of 6V. The boost capacitor should be 0.1F to 4.7F, depending on the input and output voltages, external components, and PC board layout. The boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum lowside MOSFET conduction time, which happens at maximum operating duty cycle (this occurs at minimum input voltage). In addition, ensure that the boost capacitor does not discharge to below the minimum gate-tosource voltage required to keep the high-side MOSFET fully enhanced for lowest on-resistance. This minimum gate-to-source voltage (VGS(MIN)) is determined by: VGS(MIN) = VDD x QG CBOOST 5) The parallel combination of R5 and R6, denoted R56, is calculated as: 2V R56 = - R4 10A VOUT REF CREF R4 R5 MAX8550A ILIM R6 GND where VDD is 5V, QG is the total gate charge of the high-side MOSFET, and CBOOST is the boost-capacitor value where CBOOST is C7 in the Typical Applications Circuit (Figure 8). Figure 7. Foldback Current Limit ______________________________________________________________________________________ 23 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A C1 0.01F VTT 1.25V / 1.5A C2 10F C4 60F VTTI VTT VTTS PGND2 REFIN AVDD C3 1F MAX8550A VDD R1 10 C5 4.7F VTTR 1.25V / 10mA C6 1F R3 100k VTTR VIN OVP/UVP BST D1 CMOSH-3 5V BIAS SUPPLY VIN (4.5V TO 28V) C14 470F (OPTIONAL) R2 100k POK1 POK2 C7 0.22F POK LX C8 2 x 10F SKIP TON GND SS DH C9 3.9nF C10 0.22F Q1 IRF7821 N-CHANNEL 30V, 9m L1 TOKO FDA1254-1R0M 1.0H, 21A, 1.6m 2.5V / 12A Q2 IRF7832 N-CHANNEL 30V,5m C12 150F C11 150F C11, C12 (150F, 4V, 25m, LOW-ESR POS CAPACITOR (D2E) SANYO 4TPE150M OFF C13 1F DL REF R5 20k R4 187k ILIM FB R6 41.2k OUT PGND1 SHDN ON STBY TP0 Figure 8. Typical Applications Circuit Transient Response (Buck) The inductor ripple current also affects transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: V xK L x ILOAD(MAX)2 OUT + t OFF(MIN) VIN VSAG = ( VIN - VOUT ) x K 2COUT x VOUT + t OFF(MIN) VIN where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 1. 24 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards The overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR = ILOAD(MAX)2 x L 2 x COUT x VOUT If the calculated VIN(MIN) is greater than the required minimum input voltage, then the operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. A dropout design example follows: VOUT = 2.5V fSW = 600kHz K = 1.7s tOFF(MIN) = 450ns VDROP1 = VDROP2 = 100mV h = 1.5 VIN(MIN) = 1 2.5V + 0.1V + 0.1V - 0.1V = 4.3V 1.5V x 450ns 1.7s MAX8550A Applications Information Dropout Performance (Buck) The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (see Table 1). Also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN) as much as it ramps up during the on-time (IUP). The ratio h = IUP / IDOWN indicates the controller's ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and V SAG greatly increases, unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VOUT x VDROP1 VIN(MIN) = + VDROP2 - VDROP1 h x t OFF(MIN) 1- K Voltage Positioning (Buck) In applications where fast-load transients occur, the output voltage changes instantly by RESR x COUT x ILOAD. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the output-voltage AC and DC tolerance window in tight-tolerance applications. Figure 9 shows the connection of OUT and FB in a voltage-positioned circuit. In nonvoltage-positioned circuits, the MAX8550A regulates at the output capacitor. In voltage-positioned circuits, the MAX8550A regulates on the inductor side of the voltage-positioning resistor. VOUT is reduced to: VOUT(VPS) = VOUT(NO _ LOAD) - RPOS x ILOAD PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: * Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using 25 where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the OnTime One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 1. The absolute minimum input voltage is calculated with h = 1. ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A +5V BIAS SUPPLY AVDD VDD IN BST VIN MAX8550A DH RPOS LX DL PGND1 GND VOLTAGEPOSITIONED OUTPUT FB OUT Figure 9. Voltage-Positioned Output * * * * thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. The LX and PGND1 connections to the low-side MOSFET for current sensing must be made using Kelvin-sense connections. When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes (BST, LX, DH, and DL) away from sensitive analog areas (REF, FB, and ILIM). Input ceramic capacitors must be placed as close as possible to the high-side MOSFET drain and the low-side MOSFET source. Position the MOSFETs so the impedance between the input capacitor terminals and the MOSFETs is as low as possible. Special Layout Considerations for LDO Section The capacitor (or capacitors) at VTT should be placed as close to VTT and PGND2 (pins 12 and 11) as possible to minimize the series resistance/inductance of the trace. The PGND2 side of the capacitor must be short with a low-impedance path to the exposed pad underneath the IC. The exposed pad must be star-connected to GND (pin 24), PGND1 (pin 23), and PGND2 (pin 11). A narrower trace can be used to connect the output voltage on the VTT side of the capacitor back to VTTS (pin 9). However, keep this trace well away from potentially noisy signals such as PGND1 or PGND2. This prevents noise from being injected into the error amplifier's input. For best performance, the VTTI bypass capacitor must be placed as close to VTTI (pin 13) as possible. REFIN (pin 14) should be separately routed with a clean trace and adequately bypassed to GND. Refer to the MAX8550A evaluation kit data sheet for PC board guidelines. 26 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards Typical Operating Circuit MAX8550A C1 0.01F REFIN VTTI C2 VTT 0.9V - 1.25V / 1.5A C4 VTT VTTS PGND2 VTTR 0.9V - 1.25V / 10mA C6 OVP/UVP R2 POK1 POK2 SKIP TON GND C9 SS C10 REF PGND1 R4 R5 ILIM FB R6 OUT SHDN ON STBY OFF TP0 C11 DL Q2 DH R3 POK LX Q1 VDD C5 VTTR AVDD R1 10 C3 1F 5V BIAS SUPPLY MAX8550A VIN VIN (4.5V TO 28V) BST C7 C8 L1 1.8V - 2.5V / 12A Chip Information TRANSISTOR COUNT: 5100 PROCESS: BiCMOS ______________________________________________________________________________________ 27 Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards MAX8550A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QFN THIN.EPS L 0.15 C A D2 C L D b D2/2 0.10 M C A B PIN # 1 I.D. D/2 0.15 C B k PIN # 1 I.D. 0.35x45 E/2 E2/2 E (NE-1) X e C L E2 k L DETAIL A e (ND-1) X e DETAIL B e L1 L C L C L L e 0.10 C A 0.08 C e C A1 A3 PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm 21-0140 E 1 2 28 ______________________________________________________________________________________ Integrated DDR Power-Supply Solution for Desktops, Notebooks, and Graphic Cards Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX8550A COMMON DIMENSIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T2055-2 T2055-3 T2055-4 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T3255-2 T3255-3 T3255-4 T4055-1 EXPOSED PAD VARIATIONS D2 MIN. NOM. MAX. MIN. E2 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 NOM. MAX. ALLOWED DOWN BONDS 3.00 3.00 3.00 3.00 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 3.20 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 0.30 0.40 0.50 40 10 10 - NO YES NO YES NO NO NO YES YES NO NO YES NO YES NO YES 3.30 3.40 3.20 3.30 3.40 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm 21-0140 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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